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| a FEATURES +5 V Single-Supply Operation 7 ns Propagation Delay Low Power Separate Input and Output Sections TTL and CMOS Logic Compatible Outputs Wide Output Swing TSSOP, SOIC and PDIP Packages APPLICATIONS High Speed Timing Line Receivers Data Communications High Speed V-to-F Converters Battery Operated Instrumentation High Speed Sampling Systems Window Comparators Read Channel Detection PCMCIA Cards Upgrade for MAX901 Designs Quad 7 ns Single Supply Comparator AD8564 PIN CONFIGURATIONS 16-Lead Narrow Body SO (S Suffix) R-16A -IN A +IN A GND OUT A OUT B V-ANA +IN B -IN B -IN D +IN D V+ANA OUT D OUT C V+DIG +IN C -IN C 16-Lead Epoxy DIP (P Suffix) N-16 -IN A 1 +IN A 2 + - - + 16 -IN D 15 +IN D 14 V+ANA GND 3 OUT A 4 OUT B 5 V-ANA 6 +IN B 7 -IN B 8 AD8564 + - - + 13 OUT D 12 OUT C 11 V+DIG 10 +IN C 9 -IN C AD8564 16-Lead TSSOP (RU-Suffix) RU-16 -IN A +IN A GND OUT A OUT B V-ANA +IN B -IN B 1 16 -IN D +IN D V+ANA OUT D OUT C V+DIG +IN C -IN C GENERAL DESCRIPTION AD8564 8 9 The AD8564 is quad 7 ns comparator with separate input and output supplies, thus enabling the input stage to be operated from 5 V dual supplies or a +5 V single supply while maintaining a CMOS/TTL-compatible output. Fast 7 ns propagation delay makes the AD8564 a good choice for timing circuits and line receivers. Independent analog and digital supplies provide excellent protection from supply pin interaction. The AD8564 is pin compatible with the MAX901, and has lower supply currents. All four comparators have similar propagation delays. The propagation delay for rising and falling signals is similar, and tracks over temperature and voltage. These characteristics make the AD8564 a good choice for high speed timing and data communications circuits. For a similar dual comparator with a latch function, please see the AD8598 data sheet. For a similar single comparator with latch function, please see the AD8561 data sheet. The AD8564 is specified over the industrial (-40C to +85C) temperature range. The quad AD8564 is available in the 16lead plastic DIP, narrow SO-16 surface mount, and 16-lead TSSOP packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD8564-SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage DYNAMIC PERFORMANCE Propagation Delay Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio Analog Supply Current Digital Supply Current Analog Supply Current NOTES 1 Guaranteed by design. Specifications subject to change without notice. +ANA = V+DIG = +5.0 V, V-ANA = 0 V, TA = +25 C unless otherwise noted) Conditions Min Typ 2.3 -40C TA +85C 4 VCM = 0 V -40C TA +85C VCM = 0 V 0 V VCM +3.0 V RL = 10 k 0 65 85 3000 3.0 3.5 0.3 6.75 8 4 9 3 +2.75 Max 7 8 Units mV mV V/C A A A V dB V/V pF V V ns ns ns Symbol VOS VOS/T IB IB IOS VCM CMRR AVO CIN VOH VOL tP tP tP IOH = -3.2 mA, VIN > 250 mV IOL = 3.2 mA, VIN > 250 mV 200 mV Step with 100 mV Overdrive -40C TA +85C1 100 mV Step with 5 mV Overdrive1 100 mV Step with 20 mV Overdrive1 20% to 80% 20% to 80% +4.5 V V+ANA and V+DIG +5.5 V -40C TA +85C VO = 0 V, RL = -40C TA +85C -40C TA +85C 2.4 0.4 9.8 13 0.5 3.8 1.5 80 10.5 6.0 -7.0 2.0 ns ns ns dB mA mA mA mA mA mA PSRR I+ANA IDIG I-ANA 14.0 15.6 7.0 8.0 14.0 15.6 ELECTRICAL SPECIFICATIONS (@ V Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage VOS +ANA = V+DIG = +5.0 V, V-ANA = -5 V, TA = +25 C unless otherwise noted) Conditions Min Typ 2.3 -40C TA +85C 4 VCM = 0 V -40C TA +85C VCM = 0 V 0 V VCM +3.0 V RL = 10 k -4.9 65 85 3000 3.0 3.6 0.2 4 9 3 +3.5 Max 7 8 Units mV mV V/C A A A V dB V/V pF V V Symbol VOS/T IB IB IOS VCM CMRR AVO CIN VOH VOL IOH = -3.2 mA, VIN > 250 mV IOL = 3.2 mA, VIN > 250 mV 2.6 0.3 -2- REV. A AD8564 Parameter DYNAMIC PERFORMANCE Propagation Delay Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio Analog Supply Current Digital Supply Current Analog Supply Current NOTES 1 Guaranteed by design. Specifications subject to change without notice. Symbol tP tP tP Conditions 200 mV Step with 100 mV Overdrive -40C TA +85C1 100 mV Step with 5 mV Overdrive1 100 mV Step with 20 mV Overdrive1 20% to 80% 20% to 80% +4.5 V V+ANA and V+DIG +5.5 V -40C TA +85C VO = 0 V, RL = -40C TA +85C -40C TA +85C Min Typ 6.75 8 8 Max 9.8 13 Units ns ns ns 0.5 3 3 50 70 10.8 3.6 -8.2 2.0 ns ns ns dB mA mA mA mA mA mA PSRR I+ANA IDIG I-ANA 14.0 15.6 4.4 5.6 14.0 15.6 ABSOLUTE MAXIMUM RATINGS Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +14 V Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Analog Positive Supply-Digital Positive Supply . . . . . -600 mV Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 8 V Output Short-Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Junction Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300C Package Type 16-Lead Plastic DIP (N) 16-Lead Narrow Body SO (R) 16-Lead TSSOP (RU) JA 2 JC Units C/W C/W C/W 90 113 180 47 37 37 NOTES 1 The analog input voltage is equal to 7 V or the analog supply voltage, whichever is less. 2 JA is specified for the worst case conditions, i.e., JA is specified for device in socket for, P-DIP, and JA is specified for device soldered in circuit board for SOIC and TSSOP packages. ORDERING GUIDE Model AD8564AN AD8564AR AD8564ARU Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead Plastic DIP 16-Lead Narrow Body SOIC 16-Lead Thin Shrink Small Outline (TSSOP) Package Options N-16 R-16A RU-16 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8564 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A -3- AD8564 -Typical Performance Characteristics 1.000 0.000 (V+ ANA = V+DIG = +5 V, V- ANA = 0 V, TA = +25 C unless otherwise noted) 0 V+ANA = V+DIG = +5V V-ANA = -5V INPUT BIAS CURRENT - A INPUT OFFSET VOLTAGE - mV INPUT BIAS CURRENT - A 0.800 -1.000 -1 0.600 -2.000 -2 0.400 -3.000 -3 0.200 -4.000 -4 0.000 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C -5.000 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C -5 -7.5 -2.5 0 2.5 -5 INPUT COMMON-MODE VOLTAGE - V 5 Figure 1. Input Offset Voltage vs. Temperature Figure 2. Input Bias Current vs. Temperature Figure 3. Input Bias Current vs. Input Common-Mode Voltage 500 10 STEPSIZE = 100mV OVERDRIVE = 5mV 5.000 NUMBER OF AMPLIFIERS 400 8 OUTPUT HIGH VOLTAGE - V PROPAGATION DELAY - ns 4.400 TA = +85 C 3.800 TA = +25 C tPDHL 6 300 tPDLH 200 4 3.200 TA = -40 C 2.600 100 2 0 -5 -4 -3 -2 -1 0 1 2 3 4 INPUT OFFSET VOLTAGE - mV 5 0 -50 -25 0 25 50 75 TEMPERATURE - C 100 125 2.000 0 3 6 9 12 SOURCE CURRENT - mA 15 Figure 4. Input Offset Voltage Figure 5. Propagation Delay, tPDHL/ tPDLH vs. Temperature Figure 6. Output High Voltage, VOH vs. Source Current 0.500 I+ANA, SUPPLY CURRENT - mA 5.000 I-ANA, SUPPLY CURRENT - mA 0.000 OUTPUT LOW VOLTAGE - V 0.400 TA = -40 C 0.300 TA = +25 C 4.000 TA = +85 C 3.000 TA = +25 C 2.000 TA = -40 C 1.000 -1.000 TA = -40 C TA = +25 C -2.000 TA = +85 C -3.000 0.200 TA = +85 C 0.100 -4.000 0.00 0 3 6 9 12 SINK CURRENT - mA 15 0.000 2 6 8 10 4 V+ANA SUPPLY VOLTAGE - V 12 -5.000 2 4 6 8 10 V-ANA SUPPLY VOLTAGE - V 12 Figure 7. Output Low Voltage, VOL vs. Sink Current Figure 8. I+ANA: Analog Supply Current/Comparator vs. Supply Voltage Figure 9. I-ANA: Analog Supply Current/Comparator vs. Supply Voltage -4- REV. A AD8564 3.000 I+DIG, SUPPLY CURRENT - mA 5.000 I+ANA, SUPPLY CURRENT - mA 0.000 I-ANA, SUPPLY CURRENT - mA 2.500 4.000 V+ANA = 3.000 V+ANA = +5V 2.000 5V -1.000 V+ANA = +5V -2.000 V+ANA = 5V 2.000 TA = +85 C 1.500 TA = +25 C -3.000 1.000 TA = -40 C 0.500 1.000 -4.000 0.000 2 4 6 8 10 V+DIG SUPPLY VOLTAGE - V 12 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C -5.000 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C Figure 10. I+DIG: Digital Supply Current/Comparator vs. Supply Voltage Figure 11. I+ANA : Analog Supply Current/Comparator vs. Temperature Figure 12. I-ANA: Analog Supply Current/Comparator vs. Temperature 2.000 I+DIG, SUPPLY CURRENT - mA 1.500 1.000 0.500 0.000 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C Figure 13. I+DIG: Digital Supply Current/ Comparator vs. Temperature APPLICATIONS OPTIMIZING HIGH SPEED PERFORMANCE power supply pins to ground. These capacitors act as a charge reservoir for the device during high frequency switching. A ground plane is recommended for proper high speed performance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary current paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused from "ground bounce." A proper ground plane also minimizes the effects of stray capacitance on the circuit board. OUTPUT LOADING CONSIDERATIONS As with any high speed comparator or amplifier, proper design and layout techniques should be used to ensure optimal performance from the AD8564. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the AD8564. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the AD8564 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 k source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is slower than the 5 ns capability of the AD8564. Source impedances should be less than 1 k for the best performance. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 F electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the REV. A -5- The AD8564 output can deliver up to 40 mA of output current without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (20) TTL input logic gates, or drive a load resistance less than 100 . To ensure the best performance from the AD8564 it is important to minimize capacitive loading of the output of the device. Capacitive loads greater than 50 pF will cause ringing on the output waveform and will reduce the operating bandwidth of the comparator. Propagation delay will also increase with capacitive loads above 100 pF. AD8564 INPUT STAGE AND BIAS CURRENTS The AD8564 uses a PNP differential input stage which enables the input common-mode range to extend all the way from the negative supply rail to within 2.2 V of the positive supply rail. The input common-mode voltage can be found as the average of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken to not allow the input common-mode voltage to exceed this voltage. The input bias current for the AD8564 is 4 A. As with any PNP differential input stage, this bias current will go to zero on an input that is high and will double on an input that is low. Care should be taken in choosing resistor values to be connected to the inputs as large resistors could cause significant voltage drops due to the input bias current. The input capacitance for the AD8564 is typically 3 pF. This is measured by inserting a k source resistance to the input and measuring the change in propagation delay. USING HYSTERESIS The input signal is connected directly to the inverting input of the comparator. The output is fed back to the noninverting input through R2 and R1. The ratio of R1 to R1 + R2 establishes the width of the hysteresis window with VREF setting the center of the window, or the average switching voltage. The output will switch high when the input voltage is greater than VHI and will not switch low again until the input voltage is less than VLO as given in Equation 1: V HI = V + -1-V REF ( R1 ) R1+ R2 +V REF R1 V LO =V REF 1- R1+ R2 Where V+ is the positive supply voltage. (1) Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desirable for the output to toggle between states when the input signal is near the switching threshold. Figure 14 shows a method for configuring the AD8564 with hysteresis. COMPARATOR SIGNAL The capacitor CF can also be added to introduce a pole into the feedback network. This has the effect of increasing the amount of hysteresis at high frequencies. This can be useful when comparing a relatively slow signal in a high frequency noise environment. At frequencies greater than fP = 1 , the hysteresis 2 CF R2 window approaches VHI = V+ - 1 V and VLO = 0 V. At frequencies less than fP the threshold voltages remain as in Equation 1. R1 VREF R2 CF Figure 14. Configuring the AD8564 with Hysteresis -6- REV. A AD8564 Spice Model * AD8564 SPICE Macro-Model Typical Values * 8/98, Ver. 1.0 * TAM / ADSC * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | * | | | * | | | * | | | * | | | * | | | .SUBCKT AD8564 1 2 99 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1k RC2 6 50 1k CL1 4 6 2.5E-12 CIN 1 2 3E-12 EOS 3 1 (4,6) 1E-3 * * Reference Voltage * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RDUM 98 0 100E3 GSY 99 50 POLY(1) (99,50) 8E-3 -2.6E-3 * * Gain Stage Av=250 fp=100MHz * G1 98 20 (4.6) 0.25 R1 20 98 1E3 C1 20 98 16E-13 D1 20 21 DX D2 22 20 DX V1 99 21 DC 0.71 V2 22 50 DC 0.71 * * Output Stage * Q3 99 41 46 NOX Q4 47 42 50 NOX RB1 43 41 200 RB2 40 42 200 CB1 99 41 10p CB2 42 50 5p RO1 46 45 2E3 RO2 47 45 500 EO1 98 43 POLY(1) (20,98) 0 1 EO2 40 98 POLY(1) (20,98) 0 1 * * MODELS * .MODEL PIX PNP(BF=100,VAF=130,IS=1E-14) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-14,CJO=1E-15) negative supply | | | | | 50 Output | | | | 45 .ENDS AD8564 REV. A -7- AD8564 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Epoxy DIP (N-16) 16-Lead Narrow Body SOIC (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 1 9 8 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 SEATING (1.27) PLANE BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) 16-Lead Thin Shrink Small Outline (TSSOP) (RU-16) -8- REV. A PRINTED IN U.S.A. C3219a-2-6/99 |
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